The challenges that the micro/nanoelectronic system integration research is currently facing is a huge increase of the number of processors in a chip. The ITRS expects 250 processing elements on a chip by 2015 for the consumer market. In this context, there are very important issues to be solved:
- as the early validation of HW and SW using simulation out of reach of the current approaches, what shall we propose as alternative simulation strategies that will allow functional validation and performance/power estimation?
- as we cannot expect the average programmer to be able to get the most performance out of these huge multiprocessor system, can we help him by defining specific hardware support, such as scalable cache coherence, automated dynamic data placement, transactional memories, and so on?
- as the difficulties of HW/SW integration is unparalleled, can we provide synthesis and generation tools and methodologies to simplify and automate system integration?
To answer these questions, the activity of the System Level Synthesis Group focuses on the following themes:
- Modeling and simulation of Hardware/Software Systems
- Future MPSoC architectures
- CAD for HW/SW systems : code generation, debug and synthesis
Visit our publications page for the recent and less recent conceptual advances that we have developed on these subjects.
Open source projects
Many of the topics we work on cannot be attacked theoretically, because of complexity and scalability issues, therefore we develop software and hardware (mainly simulation models as far as hardware is concern) to prove experimentally the interest of the approaches we define. Most if not all PhD thesis defended in the group produce practical results that we deliver as GPL’ed software (or with a license similar in spirit). Visit our repository page where the open software that we develop is available.
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